Agenda (Israel) | SiFive Technical Symposium

Past Proceedings for Israel - Sep, 5, 2019

The momentum surrounding the RISC-V Instruction Set Architecture (ISA) is growing on a global scale. SiFive, the company founded by the inventors of the RISC-V architecture, has been actively promoting RISC-V based cores and custom silicon solutions throughout the world via technical symposiums that aim to enlighten and engage semiconductor and system designers. Our next SiFive Tech Symposium will be held in Tel Aviv on Thursday, September 5, 2019, and we cordially invite you to attend. This event will be highly educational and will present many opportunities for engagement within the hardware community. It will feature presentations by industry veterans, ecosystem partners and academic luminaries. Attendees will learn about the RISC-V ecosystem, and the SaaS-based approach that is enabling fast access to the custom cores, design platforms, and custom SoC solutions for emerging applications.

Please join us for the SiFive Tech Symposium in Tel Aviv on Thursday, September 5th, starting at 08:30 a.m. at Daniel Hotel Herzliya, 60 Ramot Yam Street, Herzliya, Israel 46851.

Attendance is free, and includes lunch and plenty of time to meet and network with SiFive team members and ecosystem partners.

08:30 - 08:50

Registration

08:50 - 09:00

Welcome and Introduction, by Hiren Majmudar, VP of Business Development, SiFive

09:00 - 09:30

RISC-V History and State of the Union, by Andrew Waterman, Privileged Architecture Committee Chair, RISC-V Foundation

09:30 - 10:00

Keynote: Leading Semiconductor Design Revolution, by Hiren Majmudar, VP of Business Development, SiFive

10:00 - 10:15

Incubator Focused Exclusively on Accelerating Solutions in Silicon, by Danny Biran, BD Advisor Israel, Silicon Catalyst

10:15 - 10:45

Keynote: Smart Sensing and Wireless Connectivity using RISC-V, by Moshe Sheier, VP of Marketing, CEVA

10:45 - 11:05

Accelerator Architectures for Genomics, by Leonid Yavits, Postdoctoral Research Fellow in Electrical Engineering, Technion

11:05 - 11:30

Break

11:30 - 11:50

RISC-V Core IP for Target Vertical Markets, by Jahoor Vohra, Sr. FAE, SiFive

11:50 - 12:10

SiFive 7 series RISC-V Core IP Overview, by Jahoor Vohra, Sr. FAE, SiFive

12:10 - 12:30

RISC-V Core Software Ecosystem, by Andrew Waterman, Co-Founder and Chief Engineer, SiFive

12:30 - 12:45

RISC-V Hackathon in Israel, by Amir Fridman, Sr. Director of Corporate Development and Capital Investment, Western Digital

12:45 - 13:05

Tutorial: SiFive Core Designer, by Jahoor Vohra, Sr. FAE, SiFive

13:05 - 13:20

Video: Design Your Own CPU!!

13:20 - 13:30

Closing Remarks by Hiren Majmudar, VP of Business Development, SiFive

13:30 - 15:00

Lunch and Networking

PARTNERS

SiFive Technical Symposium