AGENDA (Moscow)

Please join us for SiFive’s Technical Symposium in Moscow on Monday, May 20th, starting at 09:00 a.m. at the Holiday Inn Moscow Lesnaya, 15 Lesnaya Street Moscow 125047 Russia.

Attendance is free, and includes lunch and plenty of time to meet and network with SiFive team members and ecosystem partners.

09:00 - 10:00

Registration

10:00 - 10:10

Welcome and Introduction, by Huzefa Cutlerywala, VP of Sales EMEA, SiFive

10:10 - 10:50

RISC-V History and State of the Union, by Krste Asanovic, Chairman of RISC-V Foundation

10:50 - 11:10

Professional Development Tools for RISC-V, by Filipe Torrezan, FAE, IAR Systems

11:10 - 11:40

Keynote: Leading Semiconductor Design Revolution, by Krste Asanovic, Co-Founder and Chief Architect, SiFive

11:40 - 12:00

Break

12:00 - 12:30

SCRx Family of the RISC-V Compatible CPU IP, by Pavel Khabarov, Lead Engineer, Syntacore

12:30 - 12:50

MicroTESK for RISC-V: Test Coverage Generation and Binary Code Analysis, by Alexander Kamkin, Lead Researcher, ISP RAS

12:50 - 14:00

Lunch and Demos

14:00 - 14:20

RISC-V Core IP for Target Vertical Markets, by Jahoor Vohra, Sr. FAE, SiFive

14:20 - 14:40

RISC-V Software Ecosystem Overview, by Syntacore

14:40 - 15:00

SiFive is Embedded: Intelligence at the Edge, by Huzefa Cutlerywala, VP of Sales EMEA, SiFive

15:00 - 15:30

Keynote: Development of RISC-V in Russia, by Alexander Redkin, CEO, Syntacore

15:30 - 15:50

Break

15:50 - 16:15

Tutorial: SiFive Core Designer, by Jahoor Vohra, Sr. FAE, SiFive

16:15 - 16:40

Tutorial: Using SCR1 – Open RISC-V MCU Syntacore Kernel, Ekaterina Berezina, Senior HW Engineer, Syntacore

16:40 - 16:50

Video: Design Your Own CPU!!

16:50 - 17:00

Closing Remarks, by Alexander Redkin, Executive Director, Syntacore

17:00 - 18:00

Networking/Demos

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