Agenda (Portland)

Please join us for the SiFive Tech Symposium in Portland on Tuesday, October 22nd, starting at 8:00 a.m. at Portland Community College, Willow Creek Center, 241 SW Edgeway Drive (near SW 185th and Baseline Road), Beaverton, OR 97006.

Attendance is free, and includes lunch and plenty of time to meet and network with SiFive team members and ecosystem partners.

08:00 - 08:50

Registration

08:50 - 09:00

Welcome and Introduction, by Swamy Irrinki, Sr. Director of Marketing, SiFive

09:00 - 09:30

RISC-V History and State of the Union, by RISC-V Foundation

09:30 - 10:00

Keynote: Leading Semiconductor Design Revolution, by Jack Kang, SVP of Customer Experience, SiFive

10:00 - 10:20

Custom SoC Platform for IoT Applications, by Muhammad Ahmed, Architect, SiFive

10:20 - 10:40

Break

10:40 - 11:00

Freedom HiFive RISC-V Development Platforms, by Paul Korolov, Sr. FAE, SiFive

11:00 - 11:20

SiFive Development Tools, by Rick Leatherman, Director of Development Tools, SiFive

11:20 - 11:40

Lauterbach Debug Support for SiFive RISC-V Cores, by Bob Kupyn, Western US Manager, Lauterbach

11:40 - 12:00

Formal method based techniques & tools for building safe, secure, and reliable software & embedded systems, by Fei Xie, Professor of CS, Portland State University

12:00 - 13:00

Lunch and Demos

13:00 - 13:20

RISC-V Core IP for Target Vertical Markets, by Jack Kang, SVP of Customer Experience, SiFive

13:20 - 13:40

RISC-V Core IP Debug SW Stack, by Kevin Mills, Debug & Trace Engineer, SiFive

13:40 - 14:00

SoC IP for Target Vertical Markets, by Ketan Mehta, Director of Product Marketing, SiFive

14:00 - 14:30

Keynote: Fastest Path from Algorithm to ASIC for Applications at the Edge, by Russell Klein, RISC-V Program Director at Mentor, A Siemens Business

14:30 - 14:50

Break

14:50 - 15:10

RISC-V Custom SoC Solution for SSD Controller, by Swamy Irrinki, Sr. Director of Marketing, SiFive

15:10 - 15:40

Tutorial: SiFive Core Designer, by John Min, Sr. FAE, SiFive

15:40 - 15:10

Video: Design Your Own CPU!!

15:50 - 16:00

Closing Remarks, by Jaspi Sandhu, VP of Sales, SiFive

CO-HOST

PARTNER

AGENDA (Portland)

08:00 - 08:50

Registration

08:50 - 09:00

Welcome and Introduction, by Swamy Irrinki, Sr. Director of Marketing, SiFive

09:00 - 09:30

RISC-V History and State of the Union, by RISC-V Foundation

09:30 - 10:00

Keynote: Leading Semiconductor Design Revolution, by Jack Kang, SVP of Customer Experience, SiFive

10:00 - 10:20

Custom SoC Platform for IoT Applications, by Muhammad Ahmed, Architect, SiFive

10:20 - 10:40

Break

10:40 - 11:00

Freedom HiFive RISC-V Development Platforms, by Paul Korolov, Sr. FAE, SiFive

11:00 - 11:20

SiFive Development Tools, by Rick Leatherman, Director of Development Tools, SiFive

11:20 - 11:40

Lauterbach Debug Support for SiFive RISC-V Cores, by Bob Kupyn, Western US Manager, Lauterbach

11:40 - 12:00

Formal method based techniques & tools for building safe, secure, and reliable software & embedded systems, by Fei Xie, Professor of CS, Portland State University

12:00 - 13:00

Lunch and Demos

13:00 - 13:20

RISC-V Core IP for Target Vertical Markets, by Jack Kang, SVP of Customer Experience, SiFive

13:20 - 13:40

RISC-V Core IP Debug SW Stack, by Kevin Mills, Debug & Trace Engineer, SiFive

13:40 - 14:00

SoC IP for Target Vertical Markets, by Ketan Mehta, Director of Product Marketing, SiFive

14:00 - 14:30

Keynote: Fastest Path from Algorithm to ASIC for Applications at the Edge, by Russell Klein, RISC-V Program Director at Mentor, A Siemens Business

14:30 - 14:50

Break

14:50 - 15:10

RISC-V Custom SoC Solution for SSD Controller, by Swamy Irrinki, Sr. Director of Marketing, SiFive

15:10 - 15:40

Tutorial: SiFive Core Designer, by John Min, Sr. FAE, SiFive

15:40 - 15:10

Video: Design Your Own CPU!!

15:50 - 16:00

Closing Remarks, by Jaspi Sandhu, VP of Sales, SiFive

CO-HOST

PARTNER

© 2019 SiFive, Inc. Terms of Use Privacy Policy